myModule_tb Project Status (01/29/2012 - 15:24:33) | |||
Project File: | myModule.xise | Parser Errors: | No Errors |
Module Name: | myModule_tb | Implementation State: | Placed and Routed |
Target Device: | xc3s50a-4vq100 |
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Product Version: | ISE 12.1 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Sun Jan 29 02:03:01 2012 |