| Environment Settings | ||||
| Environment Variable | xst | ngdbuild | map | par |
| PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
| Path | C:\Xilinx\12.1\ISE_DS\ISE\lib\nt; C:\Xilinx\12.1\ISE_DS\ISE\bin\nt; C:\Xilinx\12.1\ISE_DS\PlanAhead\bin; C:\Xilinx\12.1\ISE_DS\EDK\bin\nt; C:\Xilinx\12.1\ISE_DS\EDK\lib\nt; C:\Xilinx\12.1\ISE_DS\common\bin\nt; C:\Xilinx\12.1\ISE_DS\common\lib\nt; C:\Program Files\Microchip\mplabc32\v2.02\bin; C:\Perl\bin; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\Program Files\TortoiseSVN\bin; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\Program Files\Microchip\mplabc32\v1.12\bin; C:\Program Files\QuickTime\QTSystem\; C:\MCC18\bin; C:\MCC18\mpasm; C:\Program Files\Microsoft Visual Studio 9.0\VC\bin; C:\Program Files\Microsoft Visual Studio 9.0\Common7\IDE; C:\Program Files\Microsoft Visual Studio 9.0\VC\redist\x86\Microsoft.VC90.CRT; C:\Program Files\GnuWin32\bin; C:\iverilog\bin; C:\GTKWave |
C:\Xilinx\12.1\ISE_DS\ISE\lib\nt; C:\Xilinx\12.1\ISE_DS\ISE\bin\nt; C:\Xilinx\12.1\ISE_DS\PlanAhead\bin; C:\Xilinx\12.1\ISE_DS\EDK\bin\nt; C:\Xilinx\12.1\ISE_DS\EDK\lib\nt; C:\Xilinx\12.1\ISE_DS\common\bin\nt; C:\Xilinx\12.1\ISE_DS\common\lib\nt; C:\Program Files\Microchip\mplabc32\v2.02\bin; C:\Perl\bin; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\Program Files\TortoiseSVN\bin; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\Program Files\Microchip\mplabc32\v1.12\bin; C:\Program Files\QuickTime\QTSystem\; C:\MCC18\bin; C:\MCC18\mpasm; C:\Program Files\Microsoft Visual Studio 9.0\VC\bin; C:\Program Files\Microsoft Visual Studio 9.0\Common7\IDE; C:\Program Files\Microsoft Visual Studio 9.0\VC\redist\x86\Microsoft.VC90.CRT; C:\Program Files\GnuWin32\bin; C:\iverilog\bin; C:\GTKWave |
C:\Xilinx\12.1\ISE_DS\ISE\lib\nt; C:\Xilinx\12.1\ISE_DS\ISE\bin\nt; C:\Xilinx\12.1\ISE_DS\PlanAhead\bin; C:\Xilinx\12.1\ISE_DS\EDK\bin\nt; C:\Xilinx\12.1\ISE_DS\EDK\lib\nt; C:\Xilinx\12.1\ISE_DS\common\bin\nt; C:\Xilinx\12.1\ISE_DS\common\lib\nt; C:\Program Files\Microchip\mplabc32\v2.02\bin; C:\Perl\bin; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\Program Files\TortoiseSVN\bin; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\Program Files\Microchip\mplabc32\v1.12\bin; C:\Program Files\QuickTime\QTSystem\; C:\MCC18\bin; C:\MCC18\mpasm; C:\Program Files\Microsoft Visual Studio 9.0\VC\bin; C:\Program Files\Microsoft Visual Studio 9.0\Common7\IDE; C:\Program Files\Microsoft Visual Studio 9.0\VC\redist\x86\Microsoft.VC90.CRT; C:\Program Files\GnuWin32\bin; C:\iverilog\bin; C:\GTKWave |
C:\Xilinx\12.1\ISE_DS\ISE\lib\nt; C:\Xilinx\12.1\ISE_DS\ISE\bin\nt; C:\Xilinx\12.1\ISE_DS\PlanAhead\bin; C:\Xilinx\12.1\ISE_DS\EDK\bin\nt; C:\Xilinx\12.1\ISE_DS\EDK\lib\nt; C:\Xilinx\12.1\ISE_DS\common\bin\nt; C:\Xilinx\12.1\ISE_DS\common\lib\nt; C:\Program Files\Microchip\mplabc32\v2.02\bin; C:\Perl\bin; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\Program Files\TortoiseSVN\bin; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\Program Files\Microchip\mplabc32\v1.12\bin; C:\Program Files\QuickTime\QTSystem\; C:\MCC18\bin; C:\MCC18\mpasm; C:\Program Files\Microsoft Visual Studio 9.0\VC\bin; C:\Program Files\Microsoft Visual Studio 9.0\Common7\IDE; C:\Program Files\Microsoft Visual Studio 9.0\VC\redist\x86\Microsoft.VC90.CRT; C:\Program Files\GnuWin32\bin; C:\iverilog\bin; C:\GTKWave |
| XILINX | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE |
| XILINX_DSP | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE | C:\Xilinx\12.1\ISE_DS\ISE |
| XILINX_EDK | C:\Xilinx\12.1\ISE_DS\EDK | C:\Xilinx\12.1\ISE_DS\EDK | C:\Xilinx\12.1\ISE_DS\EDK | C:\Xilinx\12.1\ISE_DS\EDK |
| XILINX_PLANAHEAD | C:\Xilinx\12.1\ISE_DS\PlanAhead | C:\Xilinx\12.1\ISE_DS\PlanAhead | C:\Xilinx\12.1\ISE_DS\PlanAhead | C:\Xilinx\12.1\ISE_DS\PlanAhead |
| Synthesis Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ifn | myModule.prj | ||
| -ifmt | mixed | MIXED | |
| -ofn | myModule | ||
| -ofmt | NGC | NGC | |
| -p | xc3s50a-4-vq100 | ||
| -top | myModule | ||
| -opt_mode | Optimization Goal | Speed | SPEED |
| -opt_level | Optimization Effort | 1 | 1 |
| -iuc | Use synthesis Constraints File | NO | NO |
| -lso | Library Search Order | myModule.lso | |
| -keep_hierarchy | Keep Hierarchy | NO | NO |
| -netlist_hierarchy | Netlist Hierarchy | as_optimized | as_optimized |
| -rtlview | Generate RTL Schematic | Yes | NO |
| -glob_opt | Global Optimization Goal | AllClockNets | ALLCLOCKNETS |
| -read_cores | Read Cores | YES | YES |
| -write_timing_constraints | Write Timing Constraints | NO | NO |
| -cross_clock_analysis | Cross Clock Analysis | NO | NO |
| -bus_delimiter | Bus Delimiter | <> | <> |
| -slice_utilization_ratio | Slice Utilization Ratio | 100 | 100% |
| -bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100% |
| -verilog2001 | Verilog 2001 | YES | YES |
| -fsm_extract | YES | YES | |
| -fsm_encoding | Auto | AUTO | |
| -safe_implementation | No | NO | |
| -fsm_style | lut | LUT | |
| -ram_extract | Yes | YES | |
| -ram_style | Auto | AUTO | |
| -rom_extract | Yes | YES | |
| -shreg_extract | YES | YES | |
| -rom_style | Auto | AUTO | |
| -auto_bram_packing | NO | NO | |
| -resource_sharing | YES | YES | |
| -async_to_sync | NO | NO | |
| -mult_style | auto | AUTO | |
| -iobuf | YES | YES | |
| -max_fanout | 500 | 500 | |
| -bufg | 24 | 24 | |
| -register_duplication | YES | YES | |
| -register_balancing | No | NO | |
| -optimize_primitives | NO | NO | |
| -use_clock_enable | Yes | YES | |
| -use_sync_set | Yes | YES | |
| -use_sync_reset | Yes | YES | |
| -iob | auto | AUTO | |
| -equivalent_register_removal | YES | YES | |
| -slice_utilization_ratio_maxmargin | 5 | 0% | |
| Translation Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -intstyle | ise | None | |
| -dd | _ngo | None | |
| -p | xc3s50a-vq100-4 | None | |
| -uc | notgate.ucf | None | |
| Map Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ir | Use RLOC Constraints | OFF | OFF |
| -cm | Optimization Strategy (Cover Mode) | area | area |
| -intstyle | ise | None | |
| -o | myModule_map.ncd | None | |
| -pr | Pack I/O Registers/Latches into IOBs | off | off |
| -p | xc3s50a-vq100-4 | None | |
| Place and Route Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -t | 1 | 1 | |
| -intstyle | ise | ||
| -ol | Place & Route Effort Level (Overall) | high | std |
| -w | true | false | |
| Operating System Information | ||||
| Operating System Information | xst | ngdbuild | map | par |
| CPU Architecture/Speed | Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz/2389 MHz | Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz/2389 MHz | Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz/2389 MHz | Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz/2389 MHz |
| Host | A | A | A | A |
| OS Name | Microsoft Windows XP Professional | Microsoft Windows XP Professional | Microsoft Windows XP Professional | Microsoft Windows XP Professional |
| OS Release | Service Pack 2 (build 2600) | Service Pack 2 (build 2600) | Service Pack 2 (build 2600) | Service Pack 2 (build 2600) |