myModule_tb Project Status (01/29/2012 - 15:24:33)
Project File: myModule.xise Parser Errors: No Errors
Module Name: myModule_tb Implementation State: Placed and Routed
Target Device: xc3s50a-4vq100
  • Errors:
 
Product Version:ISE 12.1
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSun Jan 29 02:03:01 2012

Date Generated: 01/29/2012 - 15:24:33