Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s50a
Project ID (random number) 2e2ea27bfba24820a5dc96e59a06ba5c.D68AA5D625854FE5915AD580D343A243.2 Target Package: vq100
Registration ID 178899796_0_0_754 Target Speed: -4
Date Generated 2012-01-29T15:44:46 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 2 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz CPU Speed 2389 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=2
  • AGG_IO=2
  • NUM_BONDED_IBUF=1
  • NUM_BONDED_IOB=1
NetStatistics
  • NumNets_Active=3
  • NumNodesOfType_Active_DOUBLE=2
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_INPUT=1
  • NumNodesOfType_Active_IOBOUTPUT=1
SiteStatistics
  • IBUF-DIFFSI_NDT=1
  • IOB-DIFFMLR=1
SiteSummary
  • IBUF=1
  • IBUF_DELAY_ADJ_BBOX=1
  • IBUF_INBUF=1
  • IBUF_PAD=1
  • IOB=1
  • IOB_OUTBUF=1
  • IOB_PAD=1
 
Configuration Data
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:1]
  • IBUF_DELAY_VALUE=[DLY0:1]
  • IFD_DELAY_VALUE=[DLY0:1]
  • SEL_IN=[SEL_IN:1] [SEL_IN_INV:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:1]
  • PULL=[PULLUP:1]
IOB
  • O1=[O1_INV:1] [O1:0]
IOB_OUTBUF
  • IN=[IN_INV:1] [IN:0]
  • SUSPEND=[3STATE:1]
IOB_PAD
  • DRIVEATTRBOX=[12:1]
  • IOATTRBOX=[LVCMOS25:1]
  • SLEW=[SLOW:1]
 
Pin Data
IBUF
  • I=1
  • PAD=1
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=1
  • SEL_IN=1
IBUF_INBUF
  • IN=1
  • OUT=1
IBUF_PAD
  • PAD=1
IOB
  • O1=1
  • PAD=1
IOB_OUTBUF
  • IN=1
  • OUT=1
IOB_PAD
  • PAD=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s50a-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s50a-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
arwz 2 2 0 0 0 0 0
bitgen 29 29 0 0 0 0 0
map 55 55 0 0 0 0 0
ngdbuild 45 45 0 0 0 0 0
par 55 52 3 0 0 0 0
trce 52 52 0 0 0 0 0
xst 49 48 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/wizards/arwz/awz_db_dcmgen.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/myModule_tb PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2012-01-29T01:37:15 PROP_intWbtProjectID=D68AA5D625854FE5915AD580D343A243
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.myModule_tb
PROP_AutoTop=true PROP_DevFamily=Spartan3A and Spartan3AN
PROP_xilxBitgCfg_GenOpt_BinaryFile=true PROP_DevDevice=xc3s50a
PROP_DevFamilyPMName=spartan3a PROP_DevPackage=vq100
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_OBUF=1
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_PULLUP=1
 
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=171 ms, 61892 KB
Total Signals=14
Total Nets=13
Total Blocks=3
Total Processes=10
Total Simulation Time=10 ns
Simulation Resource Usage=0.0625 sec, 281161 KB
Simulation Mode=gui
Hardware CoSim=0