myModule_tb Project Status (01/29/2012 - 15:24:33) | |||
Project File: | myModule.xise | Parser Errors: | No Errors |
Module Name: | myModule | Implementation State: | Placed and Routed |
Target Device: | xc3s50a-4vq100 |
|
No Errors |
Product Version: | ISE 12.1 |
|
No Warnings |
Design Goal: | Balanced |
|
All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
0 |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slices containing only related logic | 0 | 0 | 0% | ||
Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
Number of bonded IOBs | 2 | 68 | 2% | ||
Average Fanout of Non-Clock Nets | 1.00 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sun Jan 29 15:24:09 2012 | 0 | 0 | 0 | |
Translation Report | Current | Sun Jan 29 15:24:15 2012 | 0 | 0 | 0 | |
Map Report | Current | Sun Jan 29 15:24:25 2012 | 0 | 0 | 2 Infos (2 new) | |
Place and Route Report | Current | Sun Jan 29 15:24:33 2012 | 0 | 0 | 1 Info (1 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Sun Jan 29 02:03:01 2012 |