myModule_tb Project Status (01/29/2012 - 15:24:33)
Project File: myModule.xise Parser Errors: No Errors
Module Name: myModule Implementation State: Placed and Routed
Target Device: xc3s50a-4vq100
  • Errors:
No Errors
Product Version:ISE 12.1
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
    Number of Slices containing only related logic 0 0 0%  
    Number of Slices containing unrelated logic 0 0 0%  
Number of bonded IOBs 2 68 2%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Jan 29 15:24:09 2012000
Translation ReportCurrentSun Jan 29 15:24:15 2012000
Map ReportCurrentSun Jan 29 15:24:25 2012002 Infos (2 new)
Place and Route ReportCurrentSun Jan 29 15:24:33 2012001 Info (1 new)
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSun Jan 29 02:03:01 2012

Date Generated: 01/29/2012 - 15:24:33